Electronic chip packages have long utilized vias, solder bumps, and conductive lines (collectively referred to herein as “interconnects”) for coupling different components of the chip package. For instance, a via may extend from a first conductive line in a first layer of the chip package to a second conductive line in a second layer of the chip package. Such interconnects may be tested during or following fabrication of the chip package to verify that the interconnect has appropriately connected the first and second conductive lines with respect to one another.